DC-Voltmeter :
A basic D'Arsonval movement can be converted into a dc voltmeter by adding a series resistor known as multiplier, as shown in the figure. The function of the multiplier is to limit the current through the movement so that the current does not exceed the full scale deflection value. A dc voltmeter measures the potential difference between two points in a dc circuit or a circuit component. To measure the potential difference between two points in a dc circuit or a circuit component, a dc voltmeter is always connected across them with the proper polarity. The value of the multiplier required is calculated as follows.
Im: full scale deflection current of the movement Rm : internal resistance of movement Rs : Multiplier resistance V: full range voltage of the instrument From the circuit of Fig.
V= I m *( Rm+ Rs)
Rs = (V-ImRm)/Im
= (V/Im)-Rm
therefore Rs = (V/Im)-Rm
The multiplier limits the current through the movement, so as to not exceed the value of the full scale deflection Ifsd. The above equation is also used to further extend the range in DC voltmeter.
Multi range Voltmeter:
As in the case of an ammeter, to obtain a multi range ammeter, a number of shunts are connected
across the movement with a multi-position switch. Similarly, a dc voltmeter can be converted into a multi range voltmeter by connecting a number of resistors (multipliers) along with a range switch to provide a greater number of workable ranges. The below Figure shows a multi range voltmeter using a three position switch and three multipliers R1, R2, and R3, for voltage values V1, V2, and V3. Fig 4.2 can be further modified to multipliers connected in series string, which is a more practical arrangement of the multiplier resistors of a multi range voltmeter. In this arrangement, the multipliers are connected in a series string, and the range selector selects the appropriate amount of resistance required in series with the Movement.
This arrangement is advantageous compared to the previous one, because all multi1llier resistances except the first have the standard resistance value and are also easily available in precision tolerances. The first resistor or low range multiplier, R4, is the only special resistor which has to be specially manufactured to meet the circuit requirements.
solid state voltmeter
The below figure shows the circuit of an electronic voltmeter using an IC Op Amp 741C.This is a directly coupled very high gain amplifier. The gain of the Op Amp can be adjusted to any suitable lower value by providing appropriate resistance between its output terminal, Pin No. 6, and inverting input, Pin No. 2, to provide a negative feedback. The ratio R2 /R1 determines the gain, i.e. 101 in this case, provided by the Op Amp. The 0.1 pF capacitor across the 100 k resistance R is for stability under stray pick-ups Terminals 1 and 5 are called offset null terminals. A 10 kΩ potentiometer is connected between these two offset null terminals with its centre tap connected to a - 5V supply. This potentiometer is called zero set and is used for adjusting zero output for zero input conditions.
The two diodes used are for IC protection. Under normal conditions, they are non-conducting, as the maximum voltage across them is l0 mV. If an excessive voltage, say more than 100 mV appears across them, then depending upon the polarity of the voltage, one of the diodes conducts and protects the IC. A μA scale of 50 - 1000 μA full scale deflection can be used as an indicator. Ro is adjusted to get maximum full scale deflection.
Dual Slope Digital Voltmeter
Basic Principle:
Initially, the dual slope integrating type DVM integrates the input voltage Vi. The slope of the integrated signal is proportional to the input voltage under measurements .after certain period of time say t1 the supply of input voltage Vi is stopped, and a negative voltage -Vr of the integrator. Then the output signal of integrator will have negative slope, and is constant and also proportional to the magnitude of the input voltage.
BLOCK DIAGRAM AND WORKING:
The major blocks of a dual slope integrating type DVM (dual slope analog to digital converter) are, 1. An op-amp employed as an integrator 2. A level comparator 3. Oscillator for generating time pulses 4. Decimal counter 5. Block of logic circuitry.
Initially a pulse is applied to reset the counter and the output of flip-flop will be at logic '0'. The switch Sr is in open condition and the switch, Si is in closed condition. Now, the capacitor 'C' starts to charge. Once the output of the integrator becomes greater than zero, the output state of the comparator changes which in turn opens the AND gate .When the gate opens the output of the oscillator (clock pulses) are allowed to pass through it and applied to the counter. Now the counter counts the number of pulses fed to it. As soon as it reaches its maximum count that is the counter is preset to run for a time period r,, in this condition the maximum count will be'9999', and for the next immediate clock pulse the count changes or goes to '0000' and the flip-flop will be activated. Therefore, the output of flip flop becomes logic 'I' which in turn activates the switch drive circuitry. This makes the switch Si, to open and Sr to close (i.e., the supply of Vi will be stopped. and the supply of V is applied to the integrator) with this applied signal the output of the integrator will be a constant negative slope i.e., its output signal linearly decreases to zero. This again makes the output of the comparator to change its state which in turn closes the gate. Here, the discharging time t2 of the capacitor is proportional to the input voltage signal Vi .During this discharging period the counter indicates the count. As soon as, the negative slope reaches zero volts the comparator changes its output state to 'zero' which in turn locks the gate. Once, the output of integrator becomes zero (or the input of the comparator is zero) the counter will be stopped. And the counted pulses are displayed (which directly gives the input voltage).
From the above equation, it is clear that the measured voltage signal's accuracy does not depend on the time constant of the integrator.
Initially a pulse is applied to reset the counter and the output of flip-flop will be at logic '0'. The switch Sr is in open condition and the switch, Si is in closed condition. Now, the capacitor 'C' starts to charge. Once the output of the integrator becomes greater than zero, the output state of the comparator changes which in turn opens the AND gate .When the gate opens the output of the oscillator (clock pulses) are allowed to pass through it and applied to the counter. Now the counter counts the number of pulses fed to it. As soon as it reaches its maximum count that is the counter is preset to run for a time period r,, in this condition the maximum count will be'9999', and for the next immediate clock pulse the count changes or goes to '0000' and the flip-flop will be activated. Therefore, the output of flip flop becomes logic 'I' which in turn activates the switch drive circuitry. This makes the switch Si, to open and Sr to close (i.e., the supply of Vi will be stopped. and the supply of V is applied to the integrator) with this applied signal the output of the integrator will be a constant negative slope i.e., its output signal linearly decreases to zero. This again makes the output of the comparator to change its state which in turn closes the gate. Here, the discharging time t2 of the capacitor is proportional to the input voltage signal Vi .During this discharging period the counter indicates the count. As soon as, the negative slope reaches zero volts the comparator changes its output state to 'zero' which in turn locks the gate. Once, the output of integrator becomes zero (or the input of the comparator is zero) the counter will be stopped. And the counted pulses are displayed (which directly gives the input voltage).
From the above equation, it is clear that the measured voltage signal's accuracy does not depend on the time constant of the integrator.
Advantages
1. Depending on the requirement the accuracy and sped can be varied.
2. It can provide the output with an accuracy of +-0.005% in 100ms
3. This technique exhibits excel lent noise rejection since the integration
process eliminates both noise and super imposed A.C




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